Memory controller with programmable address configuration

Electrical computers and digital processing systems: memory – Address formation

Reexamination Certificate

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Details

C711S105000, C711S154000, C711S170000, C711S217000, C365S230010, C365S189011

Reexamination Certificate

active

06684314

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention.
The invention is related to the field of memory controllers, and in particular, to a memory controller that can be programmed with various address configurations for different memory devices.
2. Statement of the Problem
A memory controller provides a system with access to memory devices. For example, a memory controller provides the interface between a computer processor and a Dynamic Random Access Memory (DRAM). The memory controller translates control signals and addresses that pass between the system and the memory devices. Memory controllers also buffer data during data transfers between the system and the memory devices.
The memory controller uses an address configuration and a memory configuration to translate system addresses into memory addresses and memory device selections. Unfortunately, different memory devices have different address configurations, and different memory systems have different memory configurations. Thus, the memory controller must be designed to use the same address configuration and the same memory configuration as the memory devices. This requires that the specific memory devices for a memory system be selected during system design when it is difficult to predict the future availability and price of specific memory devices.
In addition, many different types of memory controllers are needed to service the many different types of memory devices. Multiple different memory controllers add complexity to memory system design. The current situation also prevents the efficient mass production of a single type of memory controller.
SUMMARY OF THE SOLUTION
The invention solves the above problems with a memory controller that uses a programmable address configuration and memory configuration to convert system addresses into memory addresses and memory device selections. Advantageously, the memory controller does not need to be designed specifically for a given memory device or system because the memory controller can be subsequently programmed with the address configuration of the selected memory devices and with the memory configuration of the selected memory system. Address configuration and memory configuration programming occurs after the memory controller is designed and is manufactured.
The memory controller comprises a programmable interface coupled to address circuitry. The programmable interface is configured to receive configuration signals into the memory controller indicating a selected address configuration. The address circuitry is configured to process system addresses based on the selected address configuration to generate memory addresses. In some examples of the invention, the configuration signals also indicate a selected memory configuration, and the address circuitry is configured to process the system addresses based on the selected memory configuration to generate memory device selections.


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Bazes et al., “A Programmable NMOS DRAM Controller for Microcomputer Systems with Dual-Port Memory and Error Checking and Correction,” pp 164-172, IEEE, 1983.*
IBM Technical Disclosure Bulletin, “Programmable Memory Controller,” pp 351-354, vol. 31, Issue No. 9, 1989.

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