Memory controller with prefetching capability

Details Memory controller with prefetching capability Memory controller with prefetching capability

2008-05-06

2008-05-06

Pough, Brian R. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000

Reexamination Certificate

active

07370152

ABSTRACT:
A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodiments, results of a prefetching operations are stored in a prefetch buffer configured to provide an automatic aging mechanism, which evicts prefetched data from time to time. The prefetched data in the prefetch buffer is released and sent back to the requester in order with respect to previous memory access requests.

REFERENCES:
patent: 6237074 (2001-05-01), Phillips et al.
patent: 2003/0229762 (2003-12-01), Maiyuran et al.
Varma, A., et al., “A Class of Prefetch Schemes for On-Chip Caches,”Proceedings of the 19th Int'l Symposium on Computer Architecture, May 1992.
Mowry, T.C., “Tolerating Latency Through Software-Controlled Data Prefetching,” Ph.D. thesis, Stanford University, Mar. 1994.
Goode, G.S., “Stache: Exploring the Benefits of Predictive Prefecthing for Instruction of Caches,” 1991.

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