Memory controller with parity generator for an I/O control unit

Details Memory controller with parity generator for an I/O control unit Memory controller with parity generator for an I/O control unit

1996-12-13

1999-12-14

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714 48, H03M 1300

Patent

active

RE0364487

ABSTRACT:
A memory controller performs parity encoding on a plurality of data strings moving between a memory connected via a read path to a data bus connected to a corresponding plurality of storage devices. A write buffer has one input for receiving data for storage in the memory and another input for receiving data from the memory for parity calculation. Two outputs of the write buffer are connected to a parity generator. Circuitry responsive to control signals from the data bus conditions the parity generator to logically and recursively combine the two outputs of the write buffer for supplying an updated parity calculation to the memory via a write path. To provide error detection and correction an ECC generator is interposed between the write path and the parity generator, and an ECC check/correction unit is interposed between the read path and control-signal-responsive circuity. The parity encoding is performed using a code that is associative and commutative.

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