Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
Reexamination Certificate
2010-10-21
2011-12-27
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Transmission facility testing
C714S719000, C714S743000
Reexamination Certificate
active
08086915
ABSTRACT:
In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
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Biswas Sukalpa
Bodrozic Luka
Chen Hao
Keller James B.
Subramanian Sridhar P.
Apple Inc.
Gaffin Jeffrey A
McMahon Daniel
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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