Memory controller with error correction memory test application

Details Memory controller with error correction memory test application Memory controller with error correction memory test application

1998-03-27

1999-09-28

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Testing

371 211, G11C 700

Patent

active

059599146

ABSTRACT:
Apparatus and method for testing of memory locations containing both test data and test check bits are provided. The apparatus includes a memory controller that communicates with memory devices. In a test mode of operation using a test mode control bit, the memory controller receives test data, together with test check bits that have values corresponding to at least some of the values of the test data. The test data and test check bits are written to desired memory locations of the memory devices. The memory controller is involved in a subsequent read of these same memory locations and receives the test data and test check bits from those previously written memory locations. The memory controller determines whether a correspondence exists between the test check bits that were written and the test check bits that were read. Any lack of correspondence is indicative of one or more memory location faults. Both the test data and the test check bits are checked for accuracy during single transfer operations and the checking of the test check bits is conducted using at least some of the values of the associated test data.

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