Memory controller with continuous page mode and method therefor

Details Memory controller with continuous page mode and method therefor Memory controller with continuous page mode and method therefor

1998-01-23

2000-10-03

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

365203, 36523008, 36523009, G06F 1206

Patent

active

061287164

ABSTRACT:
A memory controller (42) supports a mode known as continuous page mode. The memory controller (42) is coupled to a pipelined internal bus and provides control signals to an external bus to control a memory such as a dynamic random access memory (DRAM) (43). The memory controller (42) compares the page portion of a next address to the page portion of the current address. If the addresses match, the memory controller (42) keeps the page open for the next cycle. However if the addresses do not match, or if the next address is not valid at this same point in time during the first access, the memory controller (42) closes the page during the first cycle. The memory controller (42) performs continuous page mode without incurring a penalty when the page is closed.

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patent: 5241503 (1993-08-01), Cheng
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patent: 5479635 (1995-12-01), Kametani
patent: 5581513 (1996-12-01), Rao
"Fast Data Access of DRAMs by Utilizing a Queued Memory Command Buffer," IBM Technical Disclosure Bulletin vol. 35, No. 7, pp. 63-66 (1992).
Motorola, 1997, "MCF5206 ColdFire.TM. Integrated Microprocessor User's Manual", pp. 10-1--10-62.
Motorola, 1991, "Memories--Memory Device Data", pp. 2-90--2-110.

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