Memory controller with 1X/MX write capability

Details Memory controller with 1X/MX write capability Memory controller with 1X/MX write capability

2001-04-07

2004-01-13

Kim, Hong (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C327S144000, C713S501000, C365S193000, C365S194000

Reexamination Certificate

active

06678811

ABSTRACT:

FIELD OF THE INVENTION
The invention pertains to the field of memory controllers.
BACKGROUND OF THE INVENTION
The purpose of a memory controller is to field and execute memory access requests (i.e., requests to read data from, and write data to, a number of memory modules). A memory access request is typically initiated by a central processing unit (CPU), but one may also be initiated by an input/output device (I/O device).
In the past, most memory controllers have been designed to access memory modules which are read and written via common clock data transmissions. That is, data bits are transmitted between a memory controller and a number of memory modules in sync with the rising edges of the memory controller's internal clock. However, there is a current push to design memory controllers which are capable of accessing double data rate (DDR) memory modules.
A DDR memory module is one which is read and written via source synchronous data transmissions. That is, data bits are transmitted between a memory controller and a number of memory modules in sync with the rising and falling edges of a strobe, with the strobe being generated by the component which sources the data. The strobe is then used by the component which receives the data for the purpose of capturing the data. Thus, a strobe is transmitted by the memory controller during a write operation, and a strobe is transmitted by a memory module during a read operation.
SUMMARY OF THE INVENTION
As is known by those skilled in the art, the complexity of memory controllers makes them very expensive components to design, develop and verify. The inventors therefore provide below a description of a memory controller having a greater number of functional modes. By providing a memory controller with a greater number of functional modes, an application specific integrated circuit (ASIC) manufacturer can satisfy a greater number of computing applications with a single memory controller, and thus save time and expense by designing, developing and verifying a fewer number of memory controllers. From a computer manufacturing perspective, the use of a common memory controller in a variety of computer systems enables machine dependent code, printed circuit board design, et cetera to be leveraged from one computer system to the next.
In accordance with the invention, new methods and apparatus pertaining to memory controllers are disclosed herein. A portion of the methods and apparatus pertain to a memory controller's write of data to a number of memory modules.
In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may need to be written to memory at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise demultiplexers which receive data from the memory controller at twice the rate which data could be written directly to a memory module. The intermediary chip may then simultaneously transmit the demultiplexed write data to memory modules in two or more banks of memory modules.
Although the invention is not limited to DDR environments, one embodiment of the invention provides a double data rate memory controller which comprises a means for writing data and generating strobe signals at 1x double data rate memory speed, and a means for writing data and generating strobe signals at Mx double data rate memory speed (where M≧2 and x is a baseline rate at which data is written to a memory module).
Another embodiment of the invention provides memory controller driver circuitry with a data pad (which pad may form part of an interface comprising a plurality of data pads) and N data propagation circuits (where N≧2). A multiplexing stage provides data to at least N−1 of the N data propagation circuits. The multiplexing stage enables a coupling of a first data input stream to each of the N data propagation circuits when the multiplexing stage is configured in a 1x mode, and enables a coupling of different data input streams to various of the N data propagation circuits when the multiplexing stage is configured in an Mx mode (1<M≦N). Output merging circuitry alternately couples the N data propagation circuits to the data pad to thereby generate either a 1x or Mx stream of data bits at the data pad.
A third embodiment of the invention provides a method for driving data from a memory controller. The method commences with providing data pad driver circuitry of the memory controller with a first data stream when the memory controller is configured to operate in a 1x mode, and providing the data pad driver circuitry with N−1 additional data streams when the memory controller is configured to operate in an Nx mode (N≧2). The data pad driver circuitry is then clocked at an Nx rate to thereby 1) generate a 1x data stream at a data pad of the memory controller when the memory controller is configured to operate in 1x mode, and 2) generate an Nx data stream at the data pad when the memory controller is configured to operate in Nx mode.
One advantage of the memory controller and driver circuitry disclosed herein is that it adapts to driving 1x or Mx (e.g., 2x) data using relatively simple hardware. By providing a memory controller that can write data in 1x and Mx modes, a more universal memory controller may be manufactured, thus scaling to increase the range of market segments covered by the memory controller with only a minimal increase in manufacturing costs.
Another advantage of the disclosed circuitry is that it can scale to support higher bandwidth and higher capacity computer systems.
The important advantages and objectives of the above and other embodiments of the invention will be further explained in, or will become apparent from, the accompanying description, drawings and claims.


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“Preliminary Publication of JEDEC Semiconductor Memory Standards-DDR SDRAM Specification”, Aug. 1999 (73 page).
JEDEC Standard No. 79, “Double Data Rate (DDR) SDRAM Specification”, Jun. 2000 (72 pages).

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