Memory controller using time-staggered lockstep sub-channels...

Details Memory controller using time-staggered lockstep sub-channels... Memory controller using time-staggered lockstep sub-channels...

2008-06-27

2011-11-15

Patel, Kaushikkumar (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C711S157000

Reexamination Certificate

active

08060692

ABSTRACT:
Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.

REFERENCES:
patent: 7093059 (2006-08-01), Christenson
patent: 7644248 (2010-01-01), Subashchandrabose et al.
patent: 2004/0081005 (2004-04-01), Garrett et al.
patent: 2004/0093472 (2004-05-01), Dahlen et al.
patent: 2007/0260841 (2007-11-01), Hampel et al.
JEDEC Standard, DDR3 SDRAM Specification, JESD79-3A, Sep. 2007.

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