Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2007-01-30
2007-01-30
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000, C710S242000, C710S022000
Reexamination Certificate
active
10703924
ABSTRACT:
One embodiment relates to a memory controller using an independent memory controller bus in order to transfer data between two or more memories. One embodiment of a data processing system includes a system bus, a system bus master coupled to the system bus, a first memory controller for controlling a first memory, a second memory controller for controlling a second memory, and a memory controller bus operating independent of the system bus to transfer data between the first memory controller and the second memory controller. The memory controller bus may include a data bus and read, write, and acknowledge signals. In one embodiment, the first memory is a block accessible memory such as a NAND Flash memory and the second memory is a random access memory (RAM) such as an SDRAM. The second memory may include arbitration logic for arbitrating between the system bus master and the first memory controller.
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Bragdon Reginald
Chiu Joanna G.
Freescale Semiconductor Inc.
Hill Susan C.
Vo Thanh D.
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