Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2011-04-12
2011-04-12
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S082000
Reexamination Certificate
active
07924048
ABSTRACT:
A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory device, and the command/address interfaces outputs, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device. The termination control output asserts a first termination control signal on a termination control signal line coupled to the memory device to cause the memory device to either (i) couple a first termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is to be received within the memory device, or (ii) couple a second termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is not to be received within the memory device.
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Oh Kyung Suk
Shaeffer Ian P.
Le Don P
Rambus Inc.
Shemwell Charles
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