Memory controller supporting redundant synchronous memories

Details Memory controller supporting redundant synchronous memories Memory controller supporting redundant synchronous memories

2005-12-20

2005-12-20

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S011000

Reexamination Certificate

active

06978397

ABSTRACT:
A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is in communication with a host server and external peripheral devices. Each I/O control logic unit includes a processor, a memory, and a memory controller. A master I/O control logic unit services I/O transactions from the host server and the external peripheral devices. A slave I/O control logic unit operates in a quiescent state until the master I/O control logic unit experiences a memory failure. At such time, the slave I/O control logic unit resumes operation of the I/O controller. In order to facilitate the switchover from the master I/O control logic unit to the slave I/O control logic unit, the master memory controller performs concurrent memory write operations in both the master and slave memories. The concurrent memory write operations ensure that the memories in both I/O control logic units are in a consistent state in order for the switchover to occur without loss of data.

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