Memory controller supporting redundant synchronous memories

Details Memory controller supporting redundant synchronous memories Memory controller supporting redundant synchronous memories

1998-05-27

2001-06-05

Lee, Thomas (Department: 2182)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S006130, C714S005110

Reexamination Certificate

active

06243829

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to computer systems using input/output (I/O) controllers. More particularly, the invention relates to a fault tolerant I/O controller having redundant synchronous memories.
BACKGROUND OF THE INVENTION
The performance of server systems has been limited by the low bandwidth associated with I/O subsystems. Attempts to improve this performance bottleneck have been geared towards increasing the I/O bandwidth. However this causes an increase in the number of I/O interrupts received by the server. The increased number of I/O interrupts unnecessarily consumes the server's time thereby degrading the overall performance of the server.
To overcome this bottleneck, a separate I/O processor or controller is typically used to perform the tasks that would normally be performed by the server to handle I/O processing. The use of an I/O controller reduces the overhead incurred by the server to process the I/O interrupts and related I/O processing tasks thereby increasing I/O throughput and improving the performance of the server. For these reasons, most server systems utilize an I/O controller to interface between external peripheral devices and the server.
FIG. 1
illustrates an exemplary computer system
100
utilizing an I/O controller
102
. There is shown an I/O controller
102
connected to a primary peripheral component interconnect (PCI) bus
104
and to external I/O devices
106
through a small computer system interface (SCSI) channel
108
. The I/O controller
102
includes a secondary PCI bus
110
to which is connected a processor
112
, a memory controller
114
, a SCSI controller
116
, and a PCI-to-PCI bridge
118
. The PCI-to-PCI bridge
118
connects the devices coupled to the secondary PCI bus
110
with the devices connected to the primary PCI bus
104
. A host central processing unit (CPU) (not shown) is in communication with the primary PCI bus
104
. The memory controller
114
is connected to an external memory device
120
.
The processor
112
is dedicated to handling I/O requests received from the host CPU. These I/O requests can be to access data from one of the external I/O devices
106
. The SCSI controller
116
interfaces with the external I/O devices
106
to transmit and retrieve data to and from these devices
106
. The memory
120
is used as a temporary storage area to store data that is in transit between the host CPU and the external I/O devices
106
. For instance, data that is written onto an external I/O device
106
is stored in the memory
120
so that it can be encoded with parity bytes prior to storage. Likewise, data that is read from an external I/O device
106
is stored in the memory
120
so that it can be decoded before it is transmitted to the host CPU.
A drawback with the design of this particular I/O controller
102
is that it is not fault tolerant. In the event the memory
120
fails, all I/O activity ceases. Such a memory failure is apparent when an intolerable number of parity errors is detected. Since the I/O controller
102
does not have a redundant memory, all I/O activity ceases thereby severely degrading the performance of the computer system
100
. Accordingly, there exists a need for a reliable I/O controller that can accommodate memory failures.
SUMMARY OF THE INVENTION
The present invention pertains to a reliable fault-tolerant I/O controller supporting redundant synchronous memories. The I/O controller is coupled to a host server through a Fibre Channel and to external peripheral devices or data units through an Ultra2 SCSI Channel. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is coupled to the host server through the Fibre Channel link and the external peripheral devices through the Ultra2 SCSI channel.
Preferably, there are two I/O control logic units that each contain the same components and are intended to replace each other in the event one of the I/O control logic units malfunctions. A master I/O control logic unit act as the master unit receiving I/O transactions from the host server and the external peripheral devices. The slave I/O control logic unit acts a slave unit that is in a quiescent state performing small tasks until the master device becomes non-operational. The memories in each I/O control logic unit are synchronized so that in the event the master I/O control logic unit malfunctions, the slave I/O control logic unit can resume processing the I/O transactions.
Each I/O control logic unit includes a processor, a memory controller, as well as other components, coupled to a PCI bus. The memory controller in each I/O control logic unit is coupled to a memory device through a respective memory bus. The memory controller in the master I/O control logic unit performs memory write operations in both the master and slave memories. The concurrent memory write operations ensure that the memories in both I/O control logic units are in a consistent state so that the slave I/O control logic unit can resume processing without any loss of data in the event the master memory device fails.
Each memory bus includes address, control, and data signal paths that enable a memory access to a respective memory device. The master memory controller generates the address and control signals to perform a memory write access to the master and slave memory device. The data signals are received in the master I/O control unit from a processor bus. Each signal path in both I/O control units has a respective bus switch that when enabled allows the signals from the master memory bus to propagate to the slave memory bus thereby initiating a memory access in both the master and slave memory devices.
Each memory controller includes an arbitration logic unit, a bus switch control unit, and a reset and fail logic unit. The arbitration logic unit in the master memory controller controls access to the master and slave memory buses. The arbitration logic unit in the slave memory controller obtains access to the slave memory bus from the master arbitration logic unit. The bus switch control logic unit controls the operation of the respective bus switches associated with each memory bus.
Each reset and fail logic unit is used to control the operational state of the respective memory controller. When the reset and fail logic unit in the master memory controller receives an indication that the slave memory device has experienced a memory failure, the master reset and fail logic unit prepares the master memory controller to operate in sole control mode. In sole control mode, the master memory controller does not perform concurrent memory write operations to the slave memory device. When the reset and fail logic unit in the slave memory controller receives an indication that the master memory device has experienced a memory failure, the slave reset and fail logic unit prepares the slave memory controller to act as the master thereby processing the I/O activity from the server and the external peripheral devices.


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