Memory controller supporting DRAM circuits with different operat

Details Memory controller supporting DRAM circuits with different operat Memory controller supporting DRAM circuits with different operat

1997-08-13

2000-10-17

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

710 52, 710112, 710 58, 710 60, G06F 1316, G06F 13368

Patent

active

061346381

ABSTRACT:
A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.

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LSI Logic, Phase-Locked Loops: G10.TM.-p Cel-Based, 605K, 600 K, and 500K Technologies, Aug. 1996, 40 pages.

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