Memory controller, semiconductor integrated circuit, and...

Details Memory controller, semiconductor integrated circuit, and... Memory controller, semiconductor integrated circuit, and...

2006-10-17

2006-10-17

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S154000, C711S005000, C713S400000, C713S500000, C714S699000, C714S700000

Reexamination Certificate

active

07124263

ABSTRACT:
A memory controller includes a state generator configured to generate a plurality of state information signals in response to command requests associated with a plurality of banks in a memory. An enable signal generator is configured to generate a plurality of enable signals indicating whether the state information signals are valid or invalid. A bank controller is configured to generate a command based on the state information signals and the enable signals.

REFERENCES:
patent: 5754557 (1998-05-01), Andrewartha
patent: 6151682 (2000-11-01), van der Wal et al.
patent: 6661422 (2003-12-01), Valmiki et al.
patent: 2002-288037 (2002-10-01), None
patent: 2002-328837 (2002-11-01), None
patent: 2004-310394 (2004-11-01), None

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