Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2005-05-03
2005-05-03
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C713S400000, C713S500000, C713S501000, C713S600000, C711S167000, C711S154000, C711S170000, C711S105000
Reexamination Certificate
active
06889335
ABSTRACT:
Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.
REFERENCES:
patent: 4759043 (1988-07-01), Lewis
patent: 4970418 (1990-11-01), Masterson
patent: 5522064 (1996-05-01), Aldereguia et al.
patent: 5701438 (1997-12-01), Bains
patent: 5710800 (1998-01-01), Ito
patent: 5727005 (1998-03-01), Le et al.
patent: 5809340 (1998-09-01), Bertone et al.
patent: 5899570 (1999-05-01), Darmawaskita et al.
patent: 5974499 (1999-10-01), Norman et al.
patent: 6065132 (2000-05-01), Takano
patent: 6125078 (2000-09-01), Ooishi et al.
patent: 6144598 (2000-11-01), Cooper et al.
patent: 6230245 (2001-05-01), Manning
patent: 6288971 (2001-09-01), Kim
patent: 6324119 (2001-11-01), Kim
patent: 6330627 (2001-12-01), Toda
patent: 6338113 (2002-01-01), Kubo et al.
patent: 6370630 (2002-04-01), Mizuyabu et al.
patent: 6414868 (2002-07-01), Wong et al.
patent: 6424198 (2002-07-01), Wolford
patent: 6459651 (2002-10-01), Lee et al.
patent: 6480946 (2002-11-01), Tomishima et al.
patent: 6496889 (2002-12-01), Perino et al.
patent: 6530001 (2003-03-01), Lee
patent: 6532525 (2003-03-01), Aleksic et al.
patent: 6553450 (2003-04-01), Dodd et al.
patent: 20010003837 (2001-06-01), Norman et al.
patent: 20010022824 (2001-09-01), Araki
patent: 20010046163 (2001-11-01), Yanagawa
patent: 20010054135 (2001-12-01), Matsuda
patent: 20020140475 (2002-10-01), Zumkehr et al.
patent: 20020147892 (2002-10-01), Rentschler et al.
patent: 20020147896 (2002-10-01), Rentschler et al.
patent: 20020147898 (2002-10-01), Rentschler et al.
patent: 20020172079 (2002-11-01), Hargis et al.
patent: WO 9904494 (1999-01-01), None
Texas Instruments, CD4018B Counter, Data Sheet, 1998.*
Texas Instruments, SN5490 Counter, Data Sheet, 1988.*
“Preliminary Publication of JEDEC Semiconductor Memory Standards-DDR SDRAM Specification”, Aug. 1999 (73 page).
JEDEC Standard No. 79, “Double Data Rate (DDR) SDRAM Specification”, Jun. 2000 (72 pages).
Hargis Jeffrey G.
Johnson Leith L.
Rentschler Eric M.
LandOfFree
Memory controller receiver circuitry with tri-state noise... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory controller receiver circuitry with tri-state noise..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller receiver circuitry with tri-state noise... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3385014