Memory controller providing dynamic arbitration of memory...

Details Memory controller providing dynamic arbitration of memory... Memory controller providing dynamic arbitration of memory...

2005-07-26

2005-07-26

Tran, Denise (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S005000, C711S156000, C711S167000

Reexamination Certificate

active

06922770

ABSTRACT:
Embodiments of the present invention provide a memory controller comprising a front-end module, a back-end module communicatively coupled to the front-end module, and a physical interface module communicatively coupled to the back-end module. The front-end module generates a plurality of page packets from a plurality of received memory commands, wherein the order of receipt of said memory commands is preserved. The back-end module dynamically issues a next one of the plurality of page packets while issuing a current one of the plurality of page packets. The physical interface module causes a plurality of transfers according to the dynamically issued current one and next one of the plurality of page packets.

REFERENCES:
patent: 5748551 (1998-05-01), Ryan et al.
patent: 5778419 (1998-07-01), Hansen et al.
patent: 6205511 (2001-03-01), Wen
patent: 6564284 (2003-05-01), Christenson
patent: 6615326 (2003-09-01), Lin
patent: 6622225 (2003-09-01), Kessler et al.
patent: 2002/0169921 (2002-11-01), Saitoh
patent: 2003/0120855 (2003-06-01), Hatakeyama et al.

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