Memory controller prioritization scheme

Details Memory controller prioritization scheme Memory controller prioritization scheme

2011-01-25

2011-01-25

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S159000

Reexamination Certificate

active

07877558

ABSTRACT:
A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.

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