Memory controller performing a mid transaction refresh and handl

Details Memory controller performing a mid transaction refresh and handl Memory controller performing a mid transaction refresh and handl

1996-03-29

2000-09-26

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

365222, 711167, 710 35, G11C 11406

Patent

active

061254258

ABSTRACT:
A method and apparatus for performing a mid transaction refresh of DRAM and handling a suspend signal from a master. A timer is used to provide a refresh request at predetermined intervals. The refresh request is made to a DRAM state machine. The DRAM state machine performs a DRAM refresh responsive to the refresh request. The refresh is performed by manipulating the RAS and CAS signal while showing a master of the transaction a series of wait states.
The suspend signal from the master is received by a DRAM state machine. The DRAM state machine will loop within its then current state as long as the suspend signal is asserted. The RAS, CAS and other control signals are maintained in the states existing when the suspend signal was asserted unless external signals (e.g., a refresh request) force a change in state of the control signals. At least one CAS state machine handles the assertion of CAS. The CAS state machine is suspended responsive to the suspend signal and will bounce between a suspend state and a predetermined state as long as the suspend signal is asserted. The CAS state machine will be suspended if at all before the falling edge of a write transfer, or before the rising edge of a read transfer.

REFERENCES:
patent: 5265212 (1993-11-01), Bruce, II
patent: 5329629 (1994-07-01), Horst et al.
patent: 5345577 (1994-09-01), Chan et al.
patent: 5418920 (1995-05-01), Kuddes
patent: 5430680 (1995-07-01), Parris
patent: 5438666 (1995-08-01), Craft et al.
patent: 5448742 (1995-09-01), Bhattacharya
patent: 5479372 (1995-12-01), Sato et al.
patent: 5630163 (1997-05-01), Fung et al.
patent: 5636367 (1997-06-01), Stones et al.
patent: 5638529 (1997-06-01), Yee et al.
patent: 5659515 (1997-08-01), Matsuo et al.
patent: 5682498 (1997-10-01), Harness

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