Memory controller operating in a system with a variable...

Details Memory controller operating in a system with a variable... Memory controller operating in a system with a variable...

2006-02-07

2008-12-16

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S158000, C713S322000, C713S600000

Reexamination Certificate

active

07467277

ABSTRACT:
The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

REFERENCES:
patent: 5193158 (1993-03-01), Kinney et al.
patent: 6573846 (2003-06-01), Trivedi et al.
patent: 6952739 (2005-10-01), Fritz et al.

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