Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-09-21
2010-06-15
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S115000, C711S118000, C711S165000, C711SE12016, C711SE12083
Reexamination Certificate
active
07739443
ABSTRACT:
The present invention provides a memory controller which includes a host interface connected to a host apparatus and receives a first data write-in unit of reception data, a memory interface connected to nonvolatile semiconductor memory in which is written a second data write-in unit of data larger than the first data write-in unit of data, and transmits the first data write-in unit of write-in data, and a central processing unit, which writes the reception data in a temporary write-in block of the nonvolatile semiconductor memory via the memory interface, reads out from the temporary write-in block the write-in data corresponding to area data when a total amount of reception data received by the host interface has reached amount of the second data write-in unit of the area data, and writes the area data including the read-out write-in data in a target block different from the temporary write-in block.
REFERENCES:
patent: 6564286 (2003-05-01), DaCosta
patent: 7266664 (2007-09-01), Higuchi et al.
patent: 5-151094 (1993-06-01), None
patent: WO 9713204 (1997-04-01), None
Microsoft Computer Dictionary, 2002, Microsoft Press, Fifth Edition, p. 215.
Bragdon Reginald G
Gu Shawn X
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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