Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-07-12
2005-07-12
Vital, Pierre M. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
06918007
ABSTRACT:
A single read request to a memory controller generates multiple read actions along with XOR/DATUM manipulation of that read data. Fewer memory transfers are required to accomplish a RAID5/DATUM parity update. This allows for higher system performance when memory bandwidth is the limiting system component. In implementation, a read buffer with XOR capability is tightly coupled to a memory controller. New parity does not need to be stored in the controller's memory. Instead, a memory read initiates multiple reads from memory based on an address decode. The data from the reads are multiplied and XOR'd before being returned to the requestor. In the case of a PCI-X requestor, this occurs as a split-completion.
REFERENCES:
patent: 5101492 (1992-03-01), Schultz et al.
patent: 5166936 (1992-11-01), Ewert et al.
patent: 5206943 (1993-04-01), Callison et al.
patent: 5249279 (1993-09-01), Schmenk et al.
patent: 5440716 (1995-08-01), Schultz et al.
patent: 5448719 (1995-09-01), Schultz et al.
patent: 5450609 (1995-09-01), Schultz et al.
patent: 5623625 (1997-04-01), Thompson et al.
patent: 5809224 (1998-09-01), Schultz et al.
patent: 5809560 (1998-09-01), Schneider
patent: 5822584 (1998-10-01), Thompson et al.
patent: 5829019 (1998-10-01), Thompson et al.
patent: 5961652 (1999-10-01), Thompson
patent: 6058489 (2000-05-01), Schultz et al.
patent: 6092169 (2000-07-01), Murthy et al.
patent: 6161165 (2000-12-01), Solomon et al.
patent: 6341342 (2002-01-01), Thompson et al.
patent: 6370616 (2002-04-01), Callison et al.
High Speed Hardware Exclusive Or Engine for Redundant Array of Inexpensive Drives Applications, IBM Technical Disclosure Bulletin, Jan. 1995, vol. No. 38, Issue No. 1, pp. 3-8.
Patterson, David A., Gibson, Garth, and Katz, Randy H., A Case for Redundant Arrays of Inexpensive Disks (RAID), Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of Berkeley, 1988, pp. 109-116.
Alvarez, Guillermo, Burkhard, Walter A., and Cristian, Flaviu, Tolerating Multiple Failures in RAID Architectures with Optimal Storage and Uniform Declustering, Department of Computer Science and Engineering, University of California, San Diego, Nov. 1996, pp. 1-11.
Carlson Jeff M.
Chang Albert H.
Garza Christopher
Thompson Mark J.
LandOfFree
Memory controller interface with XOR operations on memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory controller interface with XOR operations on memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller interface with XOR operations on memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3379835