Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-06-15
2004-09-21
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C365S233100
Reexamination Certificate
active
06795906
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory controller, and in particular to a memory control technique supporting a plurality of different specifications of random access memory (RAM).
2. Description of the Related Art
With the increasing speed of central processing units (CPUs), the demand for high-speed dynamic RAM (DRAM) is growing and thereby various types of DRAM have been developed and put in use. A well-known type of DRAM is a synchronous DRAM (SDRAM), which transfers data synchronously with an external clock signal. In SDRAM, the data transfer timing for read and write operations is synchronized with the rising edge of the external clock signal. Current information processing systems such as personal computer (PC) systems are typically designed to use SDRAM.
As next generation DRAM, there are considered a RAMBUS® DRAM for personal computers and a double data rate (DDR) SDRAM for servers. In DDR SDRAM, the data transfer timing for read and write operations is synchronized with the rising and falling edges of the clock signal or data strobe signal. Since SDRAM employs a rising edge of the clock signal, a memory controller designed for SDRAM is not applied to DDR SDRAM. Accordingly, it is desirable to provide compatibility for both SDRAM and DDR SDRAM within the same system.
To provide such compatibility, a semiconductor memory device selectively operating in a single data rate (SDR) mode and a DDR mode has been disclosed in Japanese Patent Application Unexamined Publication Kokai No. 10-302465. More specifically, the semiconductor memory device is provided with an operation controller which selects one of the SDR mode and the DDR mode depending on an external adjustment signal. When the SDR mode is selected, pulses are generated at timing corresponding to one edge of a system clock signal. In the case of the DDR mode selected, pulses are generated at timing corresponding to both edges of the system clock signal.
However, the conventional mode selection mechanism is incorporated within the semiconductor memory device. Accordingly, memory manufacturing steps become complicated, resulting in increased cost of manufacturing. Taking into consideration progression of technical innovation in the field of memory, it is necessary to enhance general versatility and extensibility in a memory controller to handle different types of memory which may be developed in the future.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory controller and control method having general versatility and enhanced extensibility, allowing different types of memory devices to be supported.
According to the present invention, a memory controller separate from a memory device to be controlled is provided with a function of supporting different types of memory devices.
According to an aspect of the present invention, a memory controller for controlling data communication with a memory device, includes: a timing adjuster for adjusting timing of data transfer between the memory device and a data bus depending on a timing control signal; and a mode controller for controlling the timing control signal to meet timing requirements of the memory device depending on a mode selection signal inputted from outside.
The memory controller may further include a level adjuster for adjusting a voltage level of data to be transferred between the memory device and the data bus depending on a type of the memory device.
According to another aspect of the present invention, a memory controller includes: a first buffer for capturing data at a rising edge of a timing control signal; a second buffer for capturing data at a falling edge of the timing control signal; and a mode controller for controlling the timing control signal to meet timing requirements of the memory device depending on a mode selection signal inputted from outside.
The mode controller may select one of a clock signal and a data strobe signal as the timing control signal depending on the mode selection signal. In the case where the memory device is a synchronous RAM (random access memory), the mode controller selects the clock signal to supply it as the timing control signal to the first buffer. In the case where the memory device is a double data rate (DDR) synchronous RAM, the mode controller selects the data strobe signal to supply it as the timing control signal to the first and second buffers.
The memory controller may further include a level adjuster for adjusting a voltage level of data to be transferred between the memory device and the data bus depending on a type of the memory device.
According to still another aspect of the present invention, an interface device connecting a processor and a memory device through a bus, includes: a memory controller for controlling data communication with the memory device, wherein the memory controller comprises: a timing adjuster for adjusting timing of data transfer between the memory device and a data bus depending on a timing control signal; and a mode controller for controlling the timing control signal to meet timing requirements of the memory device depending on a mode selection signal inputted from outside.
According to another aspect of the present invention, a control method for controlling data communication with a memory device, includes the steps of: a) capturing data in a first buffer at a rising edge of a timing control signal; b) capturing the data in a second buffer at a falling edge of the timing control signal; and c) controlling the timing control signal to meet timing requirements of the memory device depending on a mode selection signal inputted from outside.
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Osamu Hirabayashi et al., DDR Specification High-Speed SRAM Data Bus Architecture, Electronic Information and Telecommunication Association Technical Research Report, Japan, Electronic Infomration and Telecommunication Association, V. 98, 1998, pp. 1-6.
Gossage Glenn
NEC Corporation
Young & Thompson
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