Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-04-30
2003-07-22
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S141000, C711S154000, C711S152000, C709S241000, C710S107000, C710S039000
Reexamination Certificate
active
06598140
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory controllers in computer systems. More specifically, the present invention relates to a system memory controller having a plurality of memory controller agents, wherein each memory controller agent contains a coherency controller and a memory controller capable of processing memory transactions for a single memory line.
DESCRIPTION OF THE RELATED ART
In early computer systems, memory controllers were relatively simple. Typically, a single processor of the computer system would issue a read or write transaction to a memory controller, and the memory controller would complete the transaction to main memory by performing the specified read or write operation. However, as the art of computer design has progressed, memory controllers have become significantly more complex. Processors typically include multiple levels of cache memories, with each cache memory storing a subset of the contents of main memory. Furthermore, many modern computer systems often have multiple processors and I/O units, with each processor and I/O unit have one or more cache memories and requiring access to main memory. A modern memory controller must be able to efficiently handle memory transactions from each processor and I/O unit, while keeping all cache memories coherent and arbitrating between separate memory transactions to the same memory line.
To better understand the challenges facing designers of modern memory controllers, first consider a cache memory. A cache memory is a small, high-speed buffer memory which is used to hold temporarily those portions of the contents of main memory which it is believed will be used in the near future by a processor or I/O unit. The main purpose of a cache memory is to shorten the time necessary to perform memory accesses, either for data or instruction fetches from memory or writes to memory. The information located in a cache memory may be accessed in much less time than information located in main memory. Thus, a processor or I/O unit with a cache memory needs to spend far less time waiting for instructions and operands to be fetched or stored.
A cache memory is made up of many cache lines of one or more words of data. Each cache line has associated with it an address tag that uniquely identifies the memory line of main memory of which the cache line is a copy. Each time the processor or I/O unit makes a memory reference, an address tag comparison is made to see if a copy of the requested data resides in the cache memory. If the desired memory line is not in the cache memory, the memory line is retrieved from main memory, stored in the cache memory as a cache line, and supplied to the processor or I/O unit.
In addition to using a cache memory to retrieve data from main memory, the processor or I/O unit may also write data into the cache memory, thereby delaying (or, in the case of successive writes to the cache memory, even possibly eliminating) the need to write the data to main memory. When the processor or I/O unit desires to write data to memory, the cache memory makes an address tag comparison to see if the memory line into which data is to be written resides in the cache memory. If the memory line exists in the cache memory and is being held as “exclusive” or “private”, the data is written into the cache line in the cache memory that is holding the memory line. In many systems a data “dirty bit” for the cache line is then set. The dirty bit indicates that data in the cache line is dirty (i.e., has been modified), and thus before the memory line is deleted from the cache memory the modified data must be written back to main memory. If the memory line into which data is to be written does not exist in the cache memory or is held as “shared”, the memory line must be fetched as “private” or “exclusive” into the cache memory, or the data must be written directly into the main memory.
A shared-memory multi-processor (MP) system has a potentially large number of processors and I/O units, with each processor and I/O unit having one or more cache memories. For simplicity, any processor, I/O unit, or other subsystem having one or more cache memories will be referred to herein as a cacheable entity.
When an access to memory is made in such an MP system, it is necessary to take steps to ensure the integrity of data accessed. For example, when a cacheable entity reads data from memory, it is important to determine whether an updated version of the data resides in the cache of another cacheable entity. If an updated version of the data exists, something must be done to ensure that the entity accesses the updated version of the data, and not the stale version currently stored in main memory. A mechanism that ensures that the updated version of the data is utilized in a memory reference is referred to herein as a cache coherency mechanism.
The most common cache coherency mechanism is typically referred to as a snoop mechanism. A snoop mechanism usually requires the cacheable entities to share a bus such that each cacheable entity can “snoop” the memory transactions of the other cacheable entities. However, due to electrical reasons and bandwidth concerns, only a limited number of cacheable entities can share a bus in a manner that allows transactions to be snooped. Therefore, when the number of cacheable entities in an MP system is large, snooping can no longer be effectively used for cache coherency.
The most common cache coherency mechanism for systems with a large number of cacheable entities is a directory-based cache coherency mechanism. A directory-based cache coherency mechanism typically includes a directory structure in main memory. Within the directory structure, line state information exists for each memory line within the main memory. The line state information consists of a number of bits associated with each memory line. The bits for each memory line indicate, for that memory line, the state of the memory line, such as “private” or “shared”, the cacheable entities, if any, that are currently holding copies of the memory line , and any other information relevant to that memory line.
When the memory line is held as “private” in a cache memory of a first cacheable entity, the memory line is not available for use by other cacheable entities until released by the first cacheable entity, and the first cacheable entity is allowed to modify the contents of that memory line. When the memory line is held as “shared” in the cache memories of one or more cacheable entities, the memory line is available for use by other cacheable entities as long as the other entities do not want to hold the memory line as “private”. While the line is held “shared”, the contents of the line are not allowed to be modified.
When a cacheable entity desires to access a memory line, a request is sent to the memory controller. The memory controller reads the line state information for the memory line to determine the current state of the requested memory line. If the line state information bits for the requested memory line indicate that the memory line is held as private in a cache of another cacheable entity, the memory line is recalled to the memory controller. Note that if the memory line is “dirty”, the modified contents of the memory line must also be recalled and then provided to the requesting cacheable entity. When the memory line comes back to the memory controller, the memory controller supplies the memory line to the requester, updates the memory line's line state information and, updates the data for the memory line in main memory if the memory line was dirty.
If the memory line is requested as private and the memory controller reads the line state information and finds the memory line is shared, the memory controller invalidates copies of the memory line in the cache memories of other cacheable entities (as indicated by the line state information) and then supplies the memory line to the requesting cacheable entity. The memory controller also tags the line state information of the memory line as private and update
Douglas Robert C.
McAllister Curtis R.
Bataille Pierre-Michel
Hewlett--Packard Development Company, L.P.
Plettner David A.
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