Memory controller for synchronous burst transfers

Details Memory controller for synchronous burst transfers Memory controller for synchronous burst transfers

2006-11-14

2006-11-14

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S105000

Reexamination Certificate

active

07136971

ABSTRACT:
A processing system includes a processor, a memory controller, and a memory subsystem. The memory controller includes a processor interface, a memory data interface, sequential transfer circuitry, and transaction processing logic. Randomly accessed data units of a first size are synchronously exchanged between the memory data interface of the memory controller and the memory subsystem via a transfer sequence comprising a predetermined plurality of sequential transfers of data units of a size smaller than the first size.

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