Memory controller for supporting a plurality of different...

Details Memory controller for supporting a plurality of different... Memory controller for supporting a plurality of different...

2006-04-18

2006-04-18

Vital, Pierre M. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C345S534000, C345S563000

Reexamination Certificate

active

07032092

ABSTRACT:
A common DRAM controller is provided for supporting a plurality of memory types such as double data rate or quad data rate mode or types. The controller is adapted to use a number of clock signals to process data. The controller can further delay the data for a predetermined time period and capture the same.

REFERENCES:
patent: 4523309 (1985-06-01), Piasecki et al.
patent: 6091663 (2000-07-01), Kim et al.
patent: 6611905 (2003-08-01), Grundon et al.
patent: 6625702 (2003-09-01), Rentschler et al.
patent: 6681301 (2004-01-01), Mehta et al.

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