Memory controller for padding and stripping data in response...

Details Memory controller for padding and stripping data in response... Memory controller for padding and stripping data in response...

2007-04-24

2007-04-24

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S202000, C710S066000

Reexamination Certificate

active

10741298

ABSTRACT:
A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

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Structured Computer Organization, fifth edition, By Andrew S. Tanenbuam. published 1999. pp. 5,8.

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