Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2011-06-14
2011-06-14
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S112000, C711S154000, C711S113000, C711SE12053
Reexamination Certificate
active
07962715
ABSTRACT:
A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.
REFERENCES:
patent: 6088767 (2000-07-01), Dan et al.
patent: 6178132 (2001-01-01), Chen et al.
patent: 6219763 (2001-04-01), Lentz et al.
patent: 6260127 (2001-07-01), Olarig et al.
patent: 6397292 (2002-05-01), Venkatesh et al.
patent: 6578127 (2003-06-01), Sinclair
patent: 6720643 (2004-04-01), Fox et al.
patent: 7093080 (2006-08-01), Day et al.
patent: 7293009 (2007-11-01), Jacobs et al.
patent: 2004/0133747 (2004-07-01), Coldewey
patent: 2004/0133757 (2004-07-01), Rentschler et al.
patent: 2005/0177675 (2005-08-01), Newman et al.
patent: 2008/0301256 (2008-12-01), McWilliams et al.
Bhattacharya et al., “FET Gate Structure for Nonvolatile N-Channel Read-Mostly Memory Devices,” IBM Technical Disclosure Bulletin, US IBM Corp., vol. 18, No. 6, p. 1768, 1976.
“4Mb Smart 3 Boot Block Flash Memory,” Micron Technology, Inc. (2001).
“4 MEG x 16 SyncFlash Memory,” Micron Technology, Inc. (2001).
“SyncFlash and DRAM Mail Memory Subsystems in Pentium and Windows Applications,” Micron Technology, Inc. (Mar. 2002).
Bataille Pierre-Michel
Morgan & Lewis & Bockius, LLP
Rambus Inc.
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