Memory controller for independently supporting Synchronous and A

Details Memory controller for independently supporting Synchronous and A Memory controller for independently supporting Synchronous and A

1997-10-24

1999-04-06

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711100, 711154, 711167, 36523002, 365233, G06F 1200, G06F 1300

Patent

active

058931368

ABSTRACT:
The present invention provides a method and apparatus in a memory controller coupled between a system bus and memory for independently supporting one of a Synchronous DRAM (SDRAM) and an Asynchronous DRAM (ADRAM) memory type via common signal pins. According to the preferred embodiment, the memory controller comprises memory control logic for generating both SDRAM and ADRAM memory interface signals and multiplexing means for selecting as output onto common signal pins either set of interface signals depending upon a memory type setting programmed within a configuration register. The memory control logic comprises at least a request processor in addition to two memory state machines, one for SDRAM and the other for ADRAM memory operations. When a system bus request is received by the request processor, it is assigned to a request state machine which interacts with both the SDRAM state machine and the ADRAM state machine to generate two sets of memory interface signals in addition to two sets of internal control signals. The sets of signals are input to a multiplexor provided for each type of control signals (i.e., memory interface and internal control), which multiplexors are controlled by the memory type select signal output from the configuration register. Based on the memory type setting programmed into the configuration registers, the appropriate sets of memory interface and internal control signals (i.e., either SDRAM or ADRAM) are selected for output to the memory array and to other units of the memory controller, respectively.

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