Memory controller capable of locating an open command cycle...

Details Memory controller capable of locating an open command cycle... Memory controller capable of locating an open command cycle...

2008-05-27

2008-05-27

Bragdon, Reginald G. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

Reexamination Certificate

active

07380083

ABSTRACT:
A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determination is made as to whether one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command. If one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command, the request packet having a non-precharge command proceeds. In addition, the precharge command is deferred and its dynamic offset is adjusted accordingly.

REFERENCES:
patent: 6310814 (2001-10-01), Hampel et al.
Rambus, Toshiba and Elpida Announce XDR DRAM, the world's fastest memory. Jul. 2003. Retrieved form the internet <http://www.elpida.com/en
ews/2003/07-10.html>.

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