Memory controller calibration

Details Memory controller calibration Memory controller calibration

2011-01-18

2011-01-18

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C365S191000, C365S198000

Reexamination Certificate

active

07872494

ABSTRACT:
Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.

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