Memory controller and semiconductor memory device

Details Memory controller and semiconductor memory device Memory controller and semiconductor memory device

2011-08-23

2011-08-23

Baker, Stephen M (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S773000, C714S779000

Reexamination Certificate

active

08006165

ABSTRACT:
A memory controller includes a buffer to which data, which is to be transferred to a memory, is input, an ECC parity generating unit which generates an ECC parity in units of a predetermined data length from the data which is to be transferred to the memory, and a memory interface which adds the generated ECC parity in units of the predetermined data length, and delivers the data with the ECC parity to the memory. When a data length of the data which is to be transferred to the memory is less than the predetermined data length, the ECC parity generating unit regards data of a part that is short of the predetermined data length as “0”, and generates the ECC parity from the data of less than the predetermined data length.

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