Memory controller and method of memory access sequence recorderi

Details Memory controller and method of memory access sequence recorderi Memory controller and method of memory access sequence recorderi

1996-03-22

1998-10-13

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711 5, 711105, 711150, 711151, 395872, 395877, G06F 1318, G06F 1200

Patent

active

058227725

ABSTRACT:
An improved memory controller is disclosed for accessing a computer memory, which consists of a plurality of banks of page mode memory cells and is connected to a CPU via a split transaction bus with out-of-order completion capability. The improved memory controller comprises: (a) a unified command queue for receiving a memory access command; (b) a plurality of command queues equalling in number to the number of the memory banks; (c) a dispatch logic for dispatching the memory access command into one of the command queues in accordance with which memory bank the access command is to access; (d) a selection logic for selecting one of the command queues as an active command queue to execute a command, wherein all the non-selected command queues are placed on a standby status as standby command queues; and (e) switching logic provided in the selection logic for switching the command execution from the active command queue to a standby command queue, which is made active according to a predetermined criterion, when a page miss is detected or when the active command queue is empty. The switching logic also causes one of the standby command queues to perform a row address selection when the active command queue is accessing said computer memory. With the improved memory controller, penalties associated with row miss and/or page miss are eliminated. As a result, the average memory access latency is minimized and overall memory utilization efficiency is enhanced.

REFERENCES:
patent: 4843543 (1989-06-01), Isobe
patent: 5265236 (1993-11-01), Mehring et al.
patent: 5276838 (1994-01-01), Rao et al.
patent: 5375215 (1994-12-01), Hanawa et al.
patent: 5461718 (1995-10-01), Tatosian et al.
patent: 5611041 (1997-03-01), Bril et al.
patent: 5617575 (1997-04-01), Sakakibara et al.

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