Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-09-30
1999-04-13
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711154, G06F 1316
Patent
active
058939172
ABSTRACT:
A method and apparatus for performing a system memory read initiated by a bus master. In the prior art, a memory controller monitored activity on a system memory bus to determine whether to close a page of memory. Therefore, if a stall occurred during a burst read, the system memory bus would be idle and the page of system memory would be closed. The present invention keeps the page of system memory open during the entire burst read, even if the system memory bus becomes idle. Thus, latencies involved in opening and closing the page of system memory can be avoided. The present invention opens a page of system memory when receiving a first command, indicating the initiation of a read operation, from a bus master. The page of memory is kept open during the read operation, and is closed when a second command indicating the termination of the read operation is received from the bus master.
REFERENCES:
patent: 5604883 (1997-02-01), King et al.
patent: 5649161 (1997-07-01), Andrade et al.
patent: 5664153 (1997-09-01), Farrell
Chow Christopher S.
Intel Corporation
Swann Tod R.
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