Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
2007-02-22
2010-12-14
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S718000, C714S719000, C714S733000, C714S736000, C365S200000, C365S201000, C370S333000, C398S027000
Reexamination Certificate
active
07853837
ABSTRACT:
A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to at least one of the memory devices and at least one receive circuit to receive read data from at least one of the memory devices. The BER circuit includes a request generator circuit that outputs a request for a memory transaction. A request multiplexer selectively outputs a memory request to the interface from the request generator circuit or the control circuit. A data generator circuit outputs corresponding write data. A first write multiplexer selectively outputs the write data to the interface from the data generator circuit or the control circuit. A read multiplexer selectively receives read data from the receive circuit. The data generator circuit also outputs corresponding write data to a comparator circuit via a second write multiplexer. The comparator circuit outputs an error signal in response to a comparison of the received read data and corresponding stored write data. A counter outputs a count value indicating the number of errors (or bit errors) in response to the error signal. A register interface accesses the count value in the counter and a register that output one or more select signals during a mode of operation. The register interface also allows for controlling the data generator and request generator circuits.
REFERENCES:
patent: 5623497 (1997-04-01), Shimawaki et al.
patent: 6298315 (2001-10-01), Li et al.
patent: 7177211 (2007-02-01), Zimmerman
patent: 7373561 (2008-05-01), Baumer et al.
patent: 7519886 (2009-04-01), Tsao et al.
patent: 2008/0126664 (2008-05-01), Chan et al.
Cai et al., Jitter Testing for Multi-Gigabit Backplae SerDes Techniques to Decompose and Combine Various Types of Jitter, 2002, IEEE ITC International Test Conference, p. 700-709.
Li et al. A New Method for Jitter Decomposition Through it's Distribution Tail Fitting, 1999, IEEE, ITC International Test Conference, p. 788-794.
Robert K. Morrow, Jr., Accurate CDMA BER Calculations with Low Computational Complexity, Nov. 1998, IEEE Trans. on Comm., vol. 46, No. 11, p. 1413-1417.
Fibre Channel-Methodologies for Jitter Specification, Methodology for Jitter Specification Technical Report, REV 10, Jun. 9, 1999, pp. 1-96.
Madden, et al., “System-Level BER Test and Jitter Extraction of a 6.4Gbps Parallel Chip to Chip Bus on the First Generation CELL (TM) Processor,” Rambus Inc., Los Altos, CA, EPEP 2005, 4 pages.
Madden Christopher J.
Perego Richard E.
Rambus Inc.
Tabone, Jr. John J
Vierra Magen Marcus & DeNiro LLP
LandOfFree
Memory controller and method for operating a memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory controller and method for operating a memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller and method for operating a memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4210163