Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2000-09-20
2001-08-28
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S003000
Reexamination Certificate
active
06282604
ABSTRACT:
The present invention relates generally to a memory controller for dynamic random access memory (DRAM) devices, and more particularly to a memory controller for DRAM devices that include multiple (dependent) banks of memory cells that each share sense amplifiers with one or more neighboring banks.
BACKGROUND OF THE INVENTION
A dynamic random access memory (DRAM) contains an array of storage elements, often called memory cells, each storing one bit of data At the lowest level, these elements are organized into rows and columns, where one row may be accessed at a time. From the row, certain columns are selected to perform a read or write operation.
Referring to
FIG. 1
, a single DRAM device
100
may contain multiple internal storage arrays organized as banks
102
. A bank
102
is a storage array
104
and its associated sense amp (sense amplifier) arrays
106
. The memory array in a 64 Mbit RAMBus DRAM (RDRAM) typically contains 16 banks. Each unique device, bank, and row combination is called a page.
Banks in a DRAM can be independent or dependent. Independent banks each have their own sense amp arrays, independent of all other banks. Each bank can operate independently of its adjacent banks. To reduce the width of the bank in silicon, an independent bank has two dedicated sense amp arrays, one above and one below. The sense amp arrays are attached to alternating columns in the storage array.
An independent bank can be in one of two states: open or closed. An open bank has had the contents of one row transferred to a sense amp array, from where it may be rapidly accessed by a so-called column operation. Access to a closed bank requires a row operation to transfer the contents of the desired row to the sense amp cache before the column operation, and is much slower than access to an open bank.
Referring to
FIG. 2
, there is shown a DRAM device
110
having dependent banks
112
. As shown, dependent banks share adjacent sense amp arrays
114
. For instance, neighbor banks n and n+1 share the sense amp array positioned between the DRAM cell arrays for those two banks. This reduces the area occupied by sense amplifiers because only N+1 sense amp arrays are required, instead of the 2N sense amp arrays used in the device of
FIG. 1
, where N is the number or banks. But because it shares sense amp arrays with adjacent banks (called neighbor banks or just neighbors), a dependent bank cannot operate independently of its neighbors. When a dependent bank accesses its sense amp arrays, its neighbors must be closed.
A dependent bank that is closed and has a neighbor open is said to be locked. Locked banks cannot be opened until all neighbor banks are closed. As a convenience, the DRAM's internal logic is arranged so that a precharge operation on any bank will also close its neighbor banks. In other words, whenever a bank is precharged, the sense amp arrays for both it and its neighbors are precharged. If the bank is an edge bank at the end of the bank array, three sense amp arrays are precharged, and otherwise four sense amp arrays are precharged. As a result, a locked bank can be accessed by a precharge operation, a row operation, and then a column operation.
Still referring to
FIG. 2
, a bankset is a set of two or three dependent banks. The banks at each end in a DRAM device having a dependent bank organization form a bankset with two banks, because they do not share one of their sense amp arrays. All other banks in the DRAM device must form a bankset with three banks, because they share both associated sense amp arrays.
The present invention provides a memory controller apparatus and method to control a set of DRAM devices, each DRAM device being composed of several dependent banks. Among the tasks, the memory controller is responsible for its managing and tracking the state of each bank in the system: open, closed, or (for dependent banks only) locked. From a general perspective, two types of bank control policies that a memory controller could use for managing the bank state of the banks in a multiple bank DRAM are open-page and closed-page.
The closed-page policy is to close (i.e., precharge) the bank used in a memory access operation after every access. This is simplest because there is no need to track the state of any banks. If a bank is not being used, it is closed.
The open-page policy would leave each page (i.e., row of a bank) open as long as possible. If subsequent requests frequently select the same page (this is the case for many applications) row operations are avoided and performance is improved. How long the page can be left open is limited by two factors: bank dependencies (only one page may be open in a bank at a time, and a dependent bank must be closed before opening its neighbor) and the ability of the memory controller to track which banks are open. Because of the assumed difficulties in controlling dependent bank DRAMs, prior art memory controllers have not included logic for keeping pages open as long as possible in dependent bank DRAM devices.
If it is an object of the present invention to provide a memory controller for dependent bank DRAM devices that allows each open page to remain open until another memory operation logically requires that page to be closed.
Another object of the present invention is to provide a memory controller for dependent bank DRAM devices that simultaneously accesses state information for an addressed bank and state information for its neighboring banks from a cache of bank state information, and then utilizes that information to determine the minimum number of control packets needed to service a specified memory request.
SUMMARY OF THE INVENTION
In summary, the present invention is a memory controller for controlling a plurality of dynamic memory devices (DRAM's). Each DRAM device has a plurality of adjacent dependent banks of memory cells. The memory controller has a cache. Each entry in the cache corresponds to one bank in one of the dynamic memory devices, and stores information indicating which of the dynamic memory devices the entry corresponds to, whether the bank to which the entry corresponds is open, and which row of the bank was last accessed.
Bank status lookup logic is used to access cache entries in response to a memory access request that includes a bank address, a device address and a row address. The bank status lookup logic retrieves an entry, if any, in the cache corresponding to the device address and bank address. It also simultaneously retrieves entries, if any, in the cache for banks physically adjacent to the bank identified by the device address and bank address.
Reduction logic converts the information in the retrieved cache entries into a selection signal, and a protocol state machine issues a sequence of control signals (also called row and column packets) in accordance with the selection signal. The control signals are sent to the dynamic memory devices to service the memory access request.
The reduction logic may include logic for generating update signals to indicate whether entries in the cache corresponding to banks physically adjacent to the identified bank should be updated to indicate that those banks are closed.
In one embodiment, the bank status lookup logic includes a binary decoder that decodes the bank address into a set of binary decoded signals, logic connections for left-shifting and right-shifting the binary decoded signals to generate left-shifted and right-shifted signals, OR gates for logically ORing the binary decoded signals and the left-shifted and right-shifted signals to generate a group of neighbor select signals. The logic connections and OR gates generate a group of three neighbor select signals whenever the identified bank is neither a predefined top bank nor a predefined bottom bank, and otherwise generate a group of two neighbor select signals. The neighbor select signals are used to simultaneously access cache entries potentially corresponding to the identified bank and banks physically adjacent to the identified bank.
In some embodiments the bank sta
Lane Jack A.
Pennie & Edmonds LLP
Rambus Inc.
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