Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-06-09
2011-11-22
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711SE12001
Reexamination Certificate
active
08065493
ABSTRACT:
A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).
REFERENCES:
patent: 6557053 (2003-04-01), Bass et al.
patent: 6647439 (2003-11-01), De Perthuis et al.
patent: 2002/0046251 (2002-04-01), Siegel
patent: 2004/0103218 (2004-05-01), Blumrich et al.
patent: 2005020062 (2005-03-01), None
patent: 2006059283 (2006-06-01), None
patent: 2006134550 (2006-12-01), None
PCI Express System Architecture by R. Budruk, D. Anderson & T. Shanley, MindShare Inc. Jul. 2004, pp. 82-84.
Burchard A; et al “A Real-Time Streaming Memory Controller” Design, Automation and Test in Europe, 2005. Proceedings Munich, Germany Mar. 7-11, 2005, pp. 20-25.
De Kock, E. A; et al “YAPI: Application Modeling for Signal Processing Systems” Proceedings of the Design Automation Conference, IEEE, Jun. 2000, pp. 402-405.
Hennessy, J. L; et al “Computer Architecture. A Quantitative Approach Passage” Computer Architecture. A Quantitative Approach, Morgan Kaufmann Publishers, US, 2003, pp. 435-442.
Ajanovic, J; et al “Multimedia and Quality of Service Support in PCI Express Architecture” White Paper, Intel Corporation, Sep. 19, 2002.
Solari, E; et al “The Complete PCI Express Reference; Design Implications for Hardware and Software Developers” Intel Press, 2003, pp. 74-78.
Burchard Artur Tadeusz
Chauhan Atul Pratap
Hekstra-Nowacka Ewa
Van Den Hamer Peter
Bataille Pierre-Michel
Fishburn John P
NXP B.V.
LandOfFree
Memory controller and method for coupling a network and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory controller and method for coupling a network and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller and method for coupling a network and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4297915