Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-06-09
2011-10-11
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711SE12057
Reexamination Certificate
active
08037254
ABSTRACT:
A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N; IM). The memory controller (SMC) comprises a first interface (PI) for connecting the memory controller (SMC) to the network (N; IM). The first interface (PI) is arranged for receiving and transmitting data streams (ST1-ST4). A streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (ST1-ST4) between the network (N; IM) and the memory (MEM). Said streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST1-ST4). A buffer managing unit (BMU) is provided for managing a temporarily storing of data streams (ST1-ST4) in the buffer (B) in a first and second operation mode (1OM; 2OM). In the first operation mode (1OM), data from the data streams (ST1-ST4) to be stored in the memory (MEM) are temporarily stored in the buffer (B) until a portion of the buffer (B) is occupied. In the second operation mode (2OM), after the portion of the buffer (B) is occupied, the buffer managing unit (BMU) divides the buffer (B) into a pre-fetch buffer (PFB) for buffering pre-fetched data from the memory (MEM) and a write-back buffer (WBB) for buffering data to be written back to the memory (MEM).
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Burchard Artur
Chauhan Atul P. S.
Hekstra-Nowacka Ewa
Fishburn John P
Kim Matt
NXP B.V.
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