Memory controller and method control method, and rendering...

Details Memory controller and method control method, and rendering... Memory controller and method control method, and rendering...

2000-06-21

2004-02-24

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S005000, C710S022000, C711S137000, C711S143000, C711S155000

Reexamination Certificate

active

06697882

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a rendering device for forming an image in a printer, an image output apparatus of a multi-function system, or the like, and a memory controller and memory control method used in the device.
BACKGROUND OF THE INVENTION
Since a rendering device processes a large volume of image data, memory access performance has large influences on rendering performance. In order to improve the rendering performance, an arrangement including a prefetch circuit has been proposed. Since the prefetch circuit reads out data to be processed in advance, rendering performance drop upon memory access congestion can be minimized. The arrangement including the prefetch circuit can obtain higher rendering performance than that without prefetch even when it does not suffer memory access congestion.
However, since source data, pattern data, destination data, and the like the rendering device fetches from the memory have different memory access sequences, memory accesses cannot be optimized even when these data are prefetched by a single prefetch circuit, thus disturbing improvement of the rendering performance.
Furthermore, even in the prefetch mode, if single accesses are repeated without burst mode transfer, the memory access overhead increases, thus disturbing improvement of the rendering performance of the rendering device.
For example, when a character of around 10 points, a rendering object having a size equivalent to such character, or the like is rendered at 600 dpi/1 bpp/A4 upon forming an image by a rendering device, the rendering width onto a bitmap memory ranges from 60 dots to 100 dots. With this rendering width, memory access to the bitmap memory does not often match burst boundaries. Addresses that do not match burst boundaries are divisionally accessed by a plurality of single accesses in place of the burst mode, even when they are successive addresses in a page of a DRAM. For this reason, the memory access overhead increases, thus disturbing improvement of the rendering performance of the rendering device.
When an EDODRAM is used as a memory device, since it is designed to precharge every access, the access time upon page miss is the same as that upon page hit. For example, in a printer controller which outputs an image on an A4-paper sheet in a landscape mode at a resolution of 600 dpi, a page hit occurs during rendering of a line stored in a band memory, and a page miss is highly likely to occur upon starting a new line. If an EDODRAM is used as a band memory, the access time upon page miss is the same as that upon page hit. For this reason, it is effective to prefetch the first data of the next line even upon starting a new line.
By contrast, when an SDRAM or the like is used as a memory device, a memory controller which has independent read and precharge commands, and checks a page hit/miss in units of accesses to switch whether to issue a precharge command is normally used. With this controller, the memory access latency upon page hit becomes short, and the memory access performance improves. When the conventional prefetch circuit is applied to a rendering circuit using an SDRAM, at the end of a given line (to be referred to as a current line hereinafter), an access sequence (1) to prefetch the first data in the next line, (2) to write back data at the end of the current line, (3) and to prefetch the next data in the next line are generated. Since these three memory accesses access different lines and result in a page miss, precharge commands are generated three times in correspondence with transactions, resulting in a long rendering time.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the aforementioned prior art, and has as its object to provide a memory controller and memory control method, which can optimize memory accesses to improve the memory access speed, can reduce the single access overhead, can decrease the number of times of precharge upon starting a new line in rendering, and can improve the performance of a rendering circuit, and a rendering device which improves its rendering performance using the memory controller.
In order to achieve the above object, the present invention comprises the following arrangement.
A memory access controller comprises:
processing means for issuing a transaction of memory operation together with a memory address to be designated;
a queue for storing the transaction issued by the processing means; and
control means for issuing a command to a memory by reading out the transaction stored in the queue, and controlling access to the designated address.
Alternatively, a memory access controller comprises:
processing means having a plurality of DMA controllers for respectively accessing corresponding memory areas;
arbitration means for arbitrating transactions issued by the DMA controllers of the processing means; and
control means for issuing commands to a memory on the basis of the transactions arbitrated by the arbitration means, and controlling access to designated addresses.
Alternatively, a memory access controller comprises:
a memory which can be accessed in a page mode;
prefetch means for prefetching data from the memory; and
write-back means for writing back data to the memory,
wherein when it is determined that a page miss is likely to occur as a result of a prefetch, the prefetch is postponed until the write-back means writes back immediately preceding data.
Alternatively, a rendering device comprises:
a memory;
processing means having a plurality of DMA controllers for respectively accessing a plurality of areas of the memory, and image processing means for processing image data read from the plurality of areas; and
control means for issuing commands to the memory on the basis of the transactions issued by the DMA controllers of the processing means, and controlling access to designated addresses.
Preferably, the device further comprises a queue for storing the transactions issued by the processing means, and the control means issues the commands to the memory by reading out the transactions stored in the queue, and controls access to the designated addresses.
Preferably, the processing means has, as the plurality of DMA controllers, a first controller for reading out data from an area in which generated data is to be written, and a second controller for writing back data to that area, and postpones a prefetch by the first controller until the second controller writes back immediately preceding data, when it is determined that a page miss is likely to occur as a result of the prefetch of the first controller.
Preferably, the processing means further has, as the plurality of DMA controllers, a third controller for reading out source data to be rendered, and the third controller prefetches successive addresses.
Preferably, the processing means further has, as the plurality of DMA controllers, a fourth controller for reading out a pattern to be rendered, and the fourth controller inhibits a prefetch of any more data when a width of the pattern falls within a buffer of the fourth controller. Preferably, the device further comprises means for outputting data written back by the second controller to the memory.
Preferably, the first controller checks if a prefetch of one line is complete, and determines that a page miss is likely to occur if the prefetch is complete.


REFERENCES:
patent: 5822616 (1998-10-01), Hirooka
patent: 5978866 (1999-11-01), Nain
patent: 6012106 (2000-01-01), Schumann et al.
patent: 6493774 (2002-12-01), Suzuki et al.

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