Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2002-04-29
2004-07-27
Sparks, Donald (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S103000, C711S168000, C711S169000
Reexamination Certificate
active
06769051
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a memory controller for controlling a burst-accessible external memory device. More particularly, the present invention relates to a memory controller for controlling an external memory device to be accessible even in an addressing mode that is not supported by the external memory device.
2. Description of the Background Art
With recent increase in operation speed of the processors mounted in the information processing units like personal computers and the electrical household appliances, fast access is increasingly required for the memories mounted in these apparatuses. Therefore, burst-accessible memories such as flash memory and ROM (Read Only Memory) are now increasingly developed.
FIG. 1
is a block diagram showing an exemplary structure of a burst-accessible external memory device
100
. This external memory device
100
includes a cell matrix
101
, a burst control circuit
102
for controlling addressing in burst access, an address incrementer
103
for generating an address in burst access, an address latch/decoder
104
for latching and decoding an external address or an address generated by the address incrementer
103
, a data latch
105
for latching the data that is output from the cell matrix
101
according to the decode result of the address latch/decoder
104
, an input/output (I/O) buffer
106
for receiving the external data and outputting the latched data in the data latch
105
, and a control circuit
107
for controlling data input/output and the like.
The external memory device
100
receives signals XCS#, XRS#, XWS#, XAB[
8
:
30
], CLK and XADV# from a memory controller described below. The signal XCS# is a chip select signal for making the operation of each unit within the external memory device
100
valid. The signal XRS# is a read strobe signal indicating a data output period in read access. The signal XWS# is a write strobe signal indicating a write access period.
XAB [
8
:
30
] indicates an address bus for addressing the external memory device
100
to be accessed. XAB[
8
:
30
] refers to 23 bits of the address bus XAB
8
to XAB
30
. Of XAB
8
to XAB
30
, XAB
8
represents the most significant bit, and XAB
30
represents the least significant bit.
The signal CLK is a clock signal for use within the external memory device
100
in order to generate an address in burst access. The signal XADV# is an address valid signal for receiving and latching the address on XAB[
8
:
30
] into the external memory device
100
.
XDB[
0
:
15
] indicates an external data bus for data input/output. XDB[
0
:
15
] refers to 16 bits of the data bus XDB
0
to XDB
15
. Of XDB
0
to XDB
15
, XDB
0
represents the most significant bit, and XDB
15
represents the least significant bit.
In the single access mode, the address latch/decoder
104
receives and latches an address on XAB[
8
:
30
] in response to assertion of the signal XADV#. The address latch/decoder
104
then decodes that address for output to the cell matrix
101
. The cell matrix
101
selects a memory cell according to the decode result, and output the data to the data latch
105
.
In the burst access mode, the address incrementer
103
fetches an address on XAB[
8
:
30
] in response to assertion of the signal XADV# in the first access. The address latch/decoder
104
receives the address that is output from the address incrementer
103
. The address latch/decoder
104
then decodes that address for output to the cell matrix
101
. The cell matrix
101
selects a memory cell according to the decode result, and output the data to the data latch
105
.
In the second and following accesses, the address incrementer
103
increments the address in synchronization with the signal CLK for output to the address latch/decoder
104
. The address latch/decoder
104
receives the address that is output from the address incrementer
103
. The address latch/decoder
104
then decodes that address for output to the cell matrix
101
. The cell matrix
101
selects a memory cell according to the decode result, and output the data to the data latch
105
.
The operation of the address incrementer
103
varies depending on an addressing mode supported by the external memory device
100
. Such addressing modes include: a Wrap mode that implements wraparound access capable of accessing only within a page boundary; and a Non-Wrap mode capable of accessing successive addresses regardless of the page boundary.
For example, in the case where the burst length is four words (16 bits/word), the lower address value that is output from the address incrementer
103
varies in the following manner in each of the addressing modes. Note that the starting address is 2.
Wrap mode: 2→3→0→1
Non-Wrap mode: 2→3→4→5
The control circuit
107
receives the signals XCS#, XRS# and XWS# from the memory controller, and generates a timing signal of the address latch/decoder
104
, data latch
105
and I/O buffer
106
.
FIG. 2
is a block diagram schematically showing the structure of the conventional memory controller for controlling the external memory device
100
of FIG.
1
. This memory controller
200
includes a state machine
201
for causing state transition according to the operation mode of the external memory device
100
, a wait setting register
202
in which is set the number of waits in accessing the external memory device
100
by a not-shown microprocessor or the like, a wait counter
203
for counting the number of waits that is set in the wait setting register
202
, a burst counter
204
for counting the number of accesses in the burst access mode, a control signal generation circuit
205
for generating a control signal for controlling the external memory device
100
and a bus controller
300
according to the state of the state machine
201
, and an address latch
206
for latching an address from the bus controller
300
for output to the external memory device
100
.
The memory controller
200
receives signals EIHREQ, EIHBURST, EIHBCNT[
0
:
2
] and EIHAB[
8
:
30
] from the bus controller
300
. The signal EIHREQ is a signal indicating an access request to an external bus from the bus controller
300
. The external bus herein refers to a bus connected to the right side of the memory controller
200
. The external memory device
100
and the like are connected to the external bus. An internal bus herein refers to a bus connected to the left side of the memory controller
200
.
The signal EIHBURST is a signal indicating whether the access to the external memory device
100
is burst access or not. The signal EIHBCNT[
0
:
2
] is a signal indicating the burst length in burst access. EIHAB[
8
:
30
] indicates an internal address bus on which the address for access to the external bus (access to the external memory device
100
or the like) is output.
The state machine
201
causes state transition in each operation mode with reference to the signals EIHREQ and EIHBURST, a signal WCOUNT from the wait counter
203
, and a signal BCOUNT from the burst counter
204
. State transition of the state machine
201
will be described later.
The control signal generation circuit
205
generates signals CSHACK, CSHEVLD and CSHXVLD according to the state of the state machine
201
for output to the bus controller
300
. The signal CSHACK is a signal for notifying the bus controller
300
of acknowledgement of the access request by the signal EIHREQ from the bus controller
300
. The signal CSHXVLD is a signal indicating whether the data on the external data bus (XDB[
0
:
15
]) is valid or not. The signal CSHEVLD is a signal indicating whether the data on the internal data bus (EIHDB[
0
:
15
]) is valid or not.
The control signal generation circuit
205
generates the signals XCS#, XRS#, XWS# and XADV# (which are defined
McDermott Will & Emery LLP
Peugh Brian R.
Renesas Technology Corp.
Sparks Donald
LandOfFree
Memory controller and memory control method for controlling... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory controller and memory control method for controlling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller and memory control method for controlling... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3255493