Memory controller and interface

Details Memory controller and interface Memory controller and interface

2000-07-26

2004-01-20

Auve, Glenn A. (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S244000, C710S035000, C348S718000

Reexamination Certificate

active

06681285

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a memory controller architecture, and more particularly to a processor to memory interface and a memory controller within an electronic program guide (EPG) system.
BACKGROUND OF THE INVENTION
One design of memory controllers for allowing access by multiple devices to common memories utilizes the Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB). The ASB utilizes multiple access operation. A simplified memory management controller that allows multiple device to access common memories without requiring the use of multiple access operation of the type used by AMBA would be beneficial.
SUMMARY OF THE INVENTION
A memory controller is provided that has an access priority arbiter having a memory address bus and a memory data bus for connection with one or more memories and a plurality of requester buses, each for connection to a memory requester. It also has a RAM controller for connection with a RAM connected to the memory data and address buses and/or a ROM controller for connection with a ROM connected to the memory data and address buses. Each such RAM controller and/or ROM controller are connected to the access priority arbiter with one or more control lines. The access priority arbiter receives access requests on one or more of the requester buses and grants access to the memory address and data bus to one requester bus at any one time based on logic internal to the access priority arbiter.


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