Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2008-03-18
2008-03-18
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S154000
Reexamination Certificate
active
10933282
ABSTRACT:
In order to output an active command to an SDRAM, at time t0, output of a valid row address starts and a control signal ras# enters the active state. Thereafter, a control signal cs# enters the active state at time t1. At time t3, the signal cs# returns to the negative state. At time t4when some period of time has passed after time t3, output of the valid row address stops and the signal ras# enters the negative state. Outputs of the address signal adr and the control signals ras#, cas# and we# are controlled in synchronization with a modulated clock S-clk, which is generated at the spread spectrum generator. This reduces the electromagnetic interference that is caused by the address signal adr and the control signals ras#, cas# and we#.
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Bataille Pierre-Michel
Brother Kogyo Kabushiki Kaisha
Oliff & Berridg,e PLC
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