Memory controller and decoder

Details Memory controller and decoder Memory controller and decoder

2011-04-12

2011-04-12

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S230060, C326S106000

Reexamination Certificate

active

07924606

ABSTRACT:
A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced.

REFERENCES:
patent: 7151712 (2006-12-01), Lee
patent: 2008/0049539 (2008-02-01), Miyata
patent: 2008/0080296 (2008-04-01), Lee et al.
patent: 2008/0101148 (2008-05-01), Lee
patent: I273606 (2007-02-01), None

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