Memory controller-adaptive 1T/2T timing control

Details Memory controller-adaptive 1T/2T timing control Memory controller-adaptive 1T/2T timing control

2004-11-11

2009-08-04

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C711S158000, C711S170000, C713S324000, C365S227000, C345S533000, C345S534000

Reexamination Certificate

active

07571296

ABSTRACT:
Circuits, methods, and apparatus that adaptively control1T and2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with1T or2T timing.

REFERENCES:
patent: 5109490 (1992-04-01), Arimilli et al.
patent: 5301278 (1994-04-01), Bowater et al.
patent: 5504877 (1996-04-01), Dornier
patent: 5870571 (1999-02-01), Duburcq et al.
patent: 5953215 (1999-09-01), Karabatsos
patent: 6038680 (2000-03-01), Olarig
patent: 6097662 (2000-08-01), Itou
patent: 6173344 (2001-01-01), Mohammed et al.
patent: 6434654 (2002-08-01), Story et al.
patent: 6446158 (2002-09-01), Karabatsos
patent: 6526473 (2003-02-01), Kim
patent: 6715013 (2004-03-01), Touchet
patent: 7017068 (2006-03-01), McBride et al.
patent: 2002/0038404 (2002-03-01), Ryan
US 6,438,062, 08/2002, Curtis et al. (withdrawn)
Wikipedia [1]. SIMM. Version as of Nov. 17, 2003. Accessed Jan. 7, 2007. http://en.wikipedia.org/wiki/SIMM.
Wikipedia [2]. BIOS. Version as of Nov. 10, 2003. Accessed Jan. 7, 2007. http://en.wikipedia.org/wiki/BIOS.
Wikipedia. BIOS. 2003, http://en.wikipedia.org/wiki/BIOS, 2 pages.
Wikipedia. SIMM. 2003, http://en.wikipedia.org/wiki/SIMM, 1 page.

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