Memory controller

Details Memory controller Memory controller

2001-09-26

2004-06-01

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C711S105000, C711S154000, C711S157000, C365S203000, C365S204000, C365S226000, C365S229000, C365S235000

Reexamination Certificate

active

06745279

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a memory controller, or in particular to a memory controller suitable for accessing a dynamic random access memory (DRAM) for storing image data or the like.
In recent years, with rapid extension of ownership of personal computers or the like, an increased number of DRAMs have been supplied as a main memory of the personal computers. At the same time, the price of the DRAM has decreased to such an extent that it has come to be employed also for an electronic equipment other than personal computers. The DRAM includes a synchronous DRAM (hereinafter referred to as SDRAM) which can be continuously written into and read from at higher speed in synchronism with the clock of an interface (hereinafter referred to as the burst transfer), a double data rate SDRAM (hereinafter referred to as DDR-SDRAM) having a burst transfer increased to a double speed by executing the burst transfer of the SDRAM in synchronism with both the leading edge and the trailing edge of the clock signal, and a Rambus DRAM (hereinafter referred to as RDRAM). Of these DRAMs, SDRAM can constitute an inexpensive, large-capacity memory, and therefore has come to be employed by more and more equipment. The SDRAM also has come to be used in place of the conventional expensive dedicated memory (VRAM) as a frame memory for temporarily holding the image data displayed on a display unit. The SDRAM are regulated by JEDEC Standard 21-C.
Examples of devices for accessing image data of the SDRAM include a display processing device for reading and transferring image data to a display unit and a graphic processing device for generating graphics data and writing them as image data to draw arbitrary graphics. The image data generated by a video input device can also be written and stored in the SDRAM. Further, a SDRAM can be configured as a unified memory in which a main memory and a frame memory for storing image data are integrated into a single memory. With an SDRAM configured as a unified memory, not only image data but also instruction codes and various data are accessed by processors, and therefore an efficient memory access is required.
In storing image data in a frame memory, the image data is assigned to a two-dimensional address space which is finite in horizontal and vertical directions in order to hold the image data in a data storage area. The image data are held as an arrangement in horizontal and vertical directions corresponding to a display screen (display pixels) of a display device. The image data of each pixel corresponding to the display screen is configured of several to several tens of bits, and the bit length of the image data of one pixel is determined by the data format.
In storing image data in the SDRAM as a frame memory, on the other hand, the data storage area is divided into a plurality of, say four, banks, each of which is in turn divided into several pages, and each page is assigned a row address. In setting an address in the frame memory having this configuration, the linear address mapping and the tile address mapping are employed.
The linear address mapping is a method in which assuming that a horizontal arrangement of pixel data is a line, the pixel data arranged in horizontal direction (image data corresponding to the pixels of the display screen arranged in horizontal direction) are assigned horizontally continuous addresses and all the display pixels in a line are assigned the same row address, i.e. the row address of the same page. In this case, the pixel data of a different line is assigned a different row address of the same bank, or the row address of a different bank. In other words, the pixel data of a different line are assigned a different page.
The tile address mapping, on the other hand, is a method in which the pixel data in a rectangle (hereinafter referred to as the tile) having 32 bytes in horizontal direction and 16 lines in vertical direction are assigned continuous addresses, and all the pixel data in each tile are assigned the same row address, i.e. the same page. In this case, the pixel data (image data) of a different tile are assigned a different row address of the same bank, or the row address of a different bank. In other words, the pixel data of a different tile are assigned a different page.
The SDRAM requires the refresh operation for holding data, and in accessing the SDRAM, the page to be accessed is designated by a row address, and all the data belonging to the designated page are activated by being transferred to and amplified by a sense amplifier. Of the data thus activated, only the data designated by a column address are accessed by the read or write operation. In this case, the data of the same page can be continuously accessed. For different pages, however, all the data in the sense amplifier are required to be precharged by being returned to the original page, after which all the data belonging to the page to be accessed are activated by being transferred to and amplified by a sense amplifier.
In this way, the data belonging to the same page can be continuously accessed, and therefore the access efficiency can be improved. When accessing a different page, however, a page mishit occurs. In this case, the page to be accessed is precharged and activated before being accessed, resulting in a lower memory access efficiency. In accessing the SDRAM, therefore, a page mishit is desirably reduced, and in setting the address mapping in the SDRAM, the requirements of the device functions must be met.
Specifically, assume an application of the linear address mapping to the SDRAM used for a display processing device. In view of the fact that the display processing device makes access in one direction either from left to right or from right to left on a line, a page mishit is not caused and can be suppressed as long as the same line is being accessed. In an application of the tile address mapping to the SDRAM used for the display processing device, however, a page mishit is often caused. This is by reason of the fact that the display processing device can start access with an arbitrary address, and the scroll of the image displayed and the boundaries of a plurality of display image planes (hereinafter referred to as the planes) are set at arbitrary positions. An access from the display processing device to the pixel data continuous along a line of the SDRAM using the tile address mapping, therefore, goes over the tile boundary (the boundary between tiles). Thus, a page mishit occurs each time a tile boundary is crossed, resulting in a reduced memory access efficiency.
In the case where a graphic processing device accesses the SDRAM using the linear address mapping, in contrast, the continuous access is possible and the page mishit can be reduced for horizontal drawing. In the case of vertical or diagonal plotting, however, a different page is accessed for each cycle, and therefore a page mishit occurs for each drawing cycle, thereby reducing the memory access efficiency.
Specifically, the graphic processing device is adapted to generate arbitrary graphics in accordance with a draw instruction code given and write the image data on the generated graphics in a two-dimensional address space of the SDRAM. Also, the graphics drawn are configured of straight lines and curves of arbitrary angles. Therefore, the addresses to be accessed are continuous in horizontal direction, in vertical direction or in diagonal direction. As a result, as long as the tile address mapping is set in the SDRAM used for the graphic processing device, a page mishit occurs only when crossing a tile boundary regardless of the direction of access, horizontal, vertical or diagonal. It is therefore possible to reduce the page mishit more than when using the linear address mapping. For this reason, the tile address mapping is more preferable for the graphic processing, and many equipment with a frame memory realized by the SDRAM employ the tile address mapping.
A sort of real time operation is required for reading image data by the display pr

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