Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2011-01-18
2011-01-18
Elmore, Stephen C (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S158000, C711S105000
Reexamination Certificate
active
07873797
ABSTRACT:
The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.
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Search Report Dated Apr. 1, 2005.
Brune Thomas
Freissmann Lothar
Niggemeier Tim
Elmore Stephen C
Giardino, Jr. Mark A
Lin Reitseng
Opalach Joseph J.
Shedd Robert D.
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