Memory controller

Details Memory controller Memory controller

2011-02-08

2011-02-08

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000, C370S471000, C365S189050

Reexamination Certificate

active

07886211

ABSTRACT:
A memory controller includes a first calculation circuit configured to calculate an intermediate calculated value of an error correction code by using the head byte to a specified byte of a data in a process of calculating the error correction code for the data read from a memory, a data storage circuit configured to store the intermediate calculated value, a changing circuit configured to change data in a following part of the specified byte of the data, a second calculation circuit configured to calculate another error correction code by using the intermediate calculated value and the data in the following part including the changed data, and a data transferring circuit configured to transfer the changed data and the error correction code calculated in the second calculation circuit to the memory.

REFERENCES:
patent: 4551839 (1985-11-01), Botrel et al.
patent: 6286123 (2001-09-01), Kim
patent: 6310884 (2001-10-01), Odenwald, Jr.
patent: 2005-78378 (2005-03-01), None

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