Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1996-08-16
1999-05-25
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711169, G06F 1300
Patent
active
059078634
ABSTRACT:
A memory controller is described that comprises individual control segments for controlling memory that is divided into individual pairs of memory segments. The programmable memory controller provides improved average access times for memory devices by reducing the number of wait cycles between memory operations. A common data bus is shared between the memory segments. However, each control segment provides individual sets of address and control lines to each memory segment so that control sequences can occur simultaneously between multiple control and memory segments. Accordingly, when a control sequence is in process within one segment, another control sequence can occur simultaneously in another segment. By overlapping control sequences in this fashion, the bandwidth of the data bus is increased by remaining idle less frequently. Each control segment comprises a plurality of synchronous countdown register timers. Each countdown register is loaded with a programmable value at the beginning of a control sequence within its control segment. The programmable value is subsequently decremented by a value of one (`counts down`) upon each pulse of a system clock. Each counter counts down to a value of zero and then holds that value until another memory sequence begins in the control segment. A value of zero within a counter indicates to the other control segment(s) that a particular control sequence therein can begin.
REFERENCES:
patent: 4055851 (1977-10-01), Jenkins et al.
patent: 5193165 (1993-03-01), Eikill et al.
patent: 5226010 (1993-07-01), Glider et al.
patent: 5247644 (1993-09-01), Johnson et al.
patent: 5265231 (1993-11-01), Nuwayser
patent: 5463756 (1995-10-01), Saito et al.
patent: 5548787 (1996-08-01), Okamura
patent: 5615355 (1997-03-01), Wagner
patent: 5732236 (1998-03-01), Nguyen et al.
King , Jr. Conley B.
Samuels Steven B.
Sowell John B.
Starr Mark T.
Swann Tod R.
LandOfFree
Memory control unit using preloaded values to generate optimal t does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory control unit using preloaded values to generate optimal t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory control unit using preloaded values to generate optimal t will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-409255