Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1999-02-04
2002-01-22
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S531000, C345S572000, C711S005000, C711S100000, C711S154000
Reexamination Certificate
active
06340973
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory control units, memory control methods and media containing programs for realizing the same. More particularly, the present invention relates to a unit, a method and a medium containing a program, in a circuit controlling memory in which a delay develops depending on order of access thereto such as a dynamic random access memory (DRAM) that transfers data in synchronization with an operation clock to be a basis of operation, i.e., synchronous DRAM (SDRAM), for optimizing the access order to increase an actual bus bandwidth to SDRAM.
2. Description of the Background Art
The SDRAM has been conventionally in existence as one of apparatus for storing data. In SDRAM, burst transmission that continuously transfers data in synchronization with an operation clock can be designated, and the predetermined number of bits which is the smallest unit for read and write (hereinafter, referred to as a word length) can be continuously transferred the previously-specified number of times (hereinafter, referred to as a burst length) in one clock unit. Therefore, SDRAM has excellent usability.
FIG. 27
shows a memory area of a typical SDRAM. A memory area of an SDRAM is generally divided into banks composed of a plurality of pages. The SDRAM shown in
FIG. 27
is divided into two banks, i.e., banks
0
and
1
which are each composed of “n” pages from a page
0
to a page (n−1). Each page is composed of “m” columns from a column
0
to a column (m−1). Here, n and m are both integers of not less than 1. Since data is read and written column by column, the word length is equal to the number of bits in one column. For example, one column is 8 bits, m is 512, and n is 2048.
FIG. 28
is a state-transition diagram of a typical SDRAM. The SDRAM generally comprises a “sense amplifier” in each bank. As is clear from
FIG. 28
, when data stored in a column is read or data is written into a column, data in a page including the column to be read or written is previously transferred to a sense amplifier (activate) in a bank to which the page belongs, afterwhich the data is read or written from/in the sense amplifier (hereinafter, “read and write” are simply referred to as “access”). When access is continuously made to columns included in the same page in the same bank, however, data in the corresponding page has been already transferred to the sense amplifier, and therefore it is not necessary to transfer the data again.
Moreover, when a column A included in a page A is accessed and then access is made to a column B included in a page B belonging to the same bank as the page A, it is required to transfer the contents of a sense amplifier previously holding data corresponding to the page A to the page A (precharge) once and then transfer data in the page B to the sense amplifier (activate). Accordingly, when access is continuously made to columns included in different pages in the same bank, it is required to precharge and activate, resulting in a decrease of actual transfer rates.
However, since the memory area of SDRAM is divided into a plurality of banks, the decrease of actual transfer rates can be avoided by accessing different banks in the case of continuous access and performing precharge and activation processing in each bank during accessing of the other bank.
The SDRAM is described in detail, for example, in “NEC DATASHEET, MOS Integrated Circuit &mgr; PD4516421A, 4516821A, and 45116161A for Rev.P 16M-bit Synchronous DRAM (Document number: M12939EJ3V0DS00 (3rd edition), Issue date: April 1998, N CP(K))” and “Japanese Patent Laying-Open No.6-76567: Semiconductor Memory Device and Synchronism Type Semiconductor Memory Device”.
As a memory control unit for efficiently controlling such a high-performance SDRAM, a unit as described below has been conventionally used.
FIG. 29
is a block diagram showing an example of a structure of a conventional memory control unit. In
FIG. 29
, the conventional memory control unit comprises a transfer-target unit
81
, an address generator
82
, a command generator
83
, a data processor
84
, and an SDRAM
85
.
The transfer-target unit
81
outputs commands such as a start address, a transfer size, read/write and the like to the address generator
82
, to transfer data between the SDRAM
85
. The address generator
82
generates a plurality of control signals for a start address, a burst length, read/write and the like based on the commands received from the transfer-target unit
81
, and outputs the signals to the command generator
83
. The command generator
83
generates control commands such as a clock (CLK), a row address strobe (RAS), a column address strobe (CAS), write enable (WE), addressing and the like based on the control signals received from the address generator
82
, and thereby controls the SDRAM
85
and the data processor
84
. The data processor
84
transfers read data from the SDRAM
85
to the transfer-target unit
81
according to the control commands received from the command generator
83
, and also transfers write data from the transfer-target unit
81
to the SDRAM
85
. The SDRAM
85
has features similar to those of a typical SDRAM as described above, and is controlled by the control commands acquired from the command generator
83
.
As a memory system for efficiently controlling such a high-performance SDRAM, a system as described below has been conventionally used.
FIG. 30
shows an example of a structure of a conventional memory system. In FIG.
30
,the conventional memory system comprises transfer-target units
231
to
233
, an arbiter
234
, an SDRAM controller
235
, and an SDRAM
85
.
Each of the transfer-target units
231
to
233
outputs a transfer request signal to the arbiter
234
when required to transfer data with the SDRAM
85
, and outputs transfer information to the SDRAM controller
235
when a transfer enabling signal is returned from the arbiter
234
. When acquiring a transfer request signal from any one of the transfer-target units, the arbiter
234
returns a transfer enabling signal to the transfer-target unit which outputs the transfer request signal. Moreover, when acquiring transfer request signals from a plurality of transfer-target units, the arbiter
234
selects a higher-priority signal among the transfer request signals, then returns a transfer enabling signal to the transfer-target unit which outputs the selected transfer request signal. The same processing is performed to the remaining transfer request signals which are not selected. The SDRAM controller
235
is constituted by the address generator
82
, the command generator
83
, and the data processor
84
as described above. The SDRAM controller
235
generates control commands such as CLK, RAS, CAS, WE, an access address and the like based on the transfer information from the transfer target unit, and outputs the commands to the SDRAM
85
, thereby realizing data transfer between the SDRAM
85
and the transfer-target unit which outputted the transfer information. The SDRAM
85
has features similar to those of a typical SDRAM described earlier, and is controlled by the control commands acquired from the SDRAM controller
235
.
However, in controlling the SDRAM
85
in the conventional memory control unit structured as described above (see FIG.
29
), the performance of the SDRAM can not be effectively utilized in some cases depending on conditions of data transfer.
Such case arises when, in the SDRAM
85
, where its memory area is divided into banks
0
and
1
, a total of ten pieces of data which is data a
1
and a
2
existing in the bank
0
and data b
1
to data b
8
existing in the bank
1
are continuously read across a bank boundary as shown in
FIG. 31
, for example.
In this case, the data a
2
in the bank
0
and the data b
1
in the bank
1
cannot be simultaneously read, therefore the order of commands to be issued from the command generator
83
to the SDRAM
85
is determined as shown in FIG.
32
. In
FIG. 32
, precharge comman
Furukawa Yosuke
Hirai Makoto
Kimura Kozo
Kiyohara Tokuzo
Nishida Hideshi
Matsushita Electric - Industrial Co., Ltd.
Tung Kee M.
Wenderoth , Lind & Ponack, L.L.P.
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