Memory control translators

Details Memory control translators Memory control translators

2005-05-31

2005-05-31

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

Reexamination Certificate

active

06901494

ABSTRACT:
According to one aspect of the invention, a method is provided in which one or more write commands and their corresponding write data are received from a first device. The corresponding write data may be delayed by the first device by a first delay period. The one or more write commands and their corresponding write data are stored in a set of buffers. In response to another write command being received from the first device, a buffered write command and its corresponding write data are sent to a second device for execution, without waiting for the write data corresponding to said another write command to be sent from the first device.

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