Electrical computers and digital processing systems: memory – Address formation – Slip control – misaligning – boundary alignment
Reexamination Certificate
2001-03-29
2004-03-02
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Slip control, misaligning, boundary alignment
C711S204000, C711S209000, C711S219000
Reexamination Certificate
active
06701422
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to computers and, more particularly, to memory controllers for computers. A major objective of the invention is to provide for more effective speculative addressing by a memory controller.
Much of modern progress is associated with the increasing prevalence of computers. A typical computer has memory for storing data and instructions and one or more processors (e.g., a “central processing unit” or “CPU”) for executing the instructions and manipulating data accordingly. The instructions executed by computers are relatively simple; complex tasks can be accomplished by executing programs with large numbers of instructions. The prowess of computers is largely due to the speed with which the instructions can be executed.
Advances in computer technology have provided dramatic increases in computer performance. As dramatic as the advances have been, there is an insatiable demand for more computing power. One speed bottleneck is the time it takes for data and instructions to be transferred between processor and memory. While, in principle, processor would communicate directly with memory, the rapid design cycles for both processor and memory make it difficult for the processors and memories to interface optimally upon introduction to the market.
For example, some memories provide for a paged mode in which it can be assumed that only low-order address bits need to be examined to determine a next address. Since fewer address lines need to be examined, the memory can respond to addresses more rapidly. When a page change is required, a page-boundary detection signal is to be sent to the memory, in which case the memory responds by looking at all the address bits. In general, processors are not “aware” of memory specifics, such as the presence of a page mode, so there is a problem of optimally interfacing processors and memory.
Memory controllers can be designed in a relatively short time to interface between a processor and a memory type so that the optimal memory-operating mode could be used. The presence of the memory controller adds a potential latency to memory accesses, since instead of being transmitted directly to the memory, an address asserted by a processor must be forwarded to or translated and then forwarded to the memory. On the other hand, a memory controller can speed up accesses by accessing memory in anticipation of predicted next addresses. Typically, memory addresses are accessed sequentially, so the prediction can simply involve selecting the next address in a series. Some processors indicate whether the next address is sequential or not, so the validity of the prediction is known even before the next address is received.
The predictive approach improves performance to the extent the predictions are accurate. Typically, the predictions are accurate when the addresses are sequential and do not cross page boundaries. An objective of the present invention is to provide for further performance improvements by enlarging the class of accurate predictions.
SUMMARY OF THE INVENTION
The present invention addresses two important cases of address prediction: wrapping of an address in case of crossing wrap boundaries in a burst transfer at the processor side, and crossing page boundaries at the memory side. The present invention provides a memory controller that provides predictive addresses that wrap at a programmable wrap boundary and/or provides predictive page-boundary detection signals. In one aspect the invention is a memory controller with a incrementer in the form of a programmable counter, while in another the invention is a computer system with such a memory controller. The inventive method can involve the predictive wraps, predictive page boundary detections or both.
In the case of a wrap boundary of a burst transfer, the invention provides for wrapping without interrupting the performance enhancement achieved by accurate address predictions. Where predictive page boundaries are used, a series of accurate predictions can proceed with little or no interruption across page boundaries. The predictive wraps and page boundary detections can be used together in the case of a loop that extends across page boundaries. These and other features and advantages of the invention are apparent from the description below with reference to the following drawings.
REFERENCES:
patent: 4722047 (1988-01-01), Chan et al.
patent: 5386521 (1995-01-01), Saitoh
patent: 5918252 (1999-06-01), Chen et al.
patent: 6216208 (2001-04-01), Greiner et al.
patent: 0 501 621 (1992-09-01), None
patent: 0 811 921 (1997-12-01), None
Koninklijke Philips Electronics , N.V.
Portka Gary
Zawilski Peter
LandOfFree
Memory control system with incrementer for generating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory control system with incrementer for generating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory control system with incrementer for generating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3266569